Design of age based FINFET for CPU switch applications

Abstract

The field of microelectronics experienced a huge shift from the traditional planar MOSFET to 3D multi-gated structures, most noticeable being the FinFET. FinFET is regarded the most favourable for progressing CMOS downscalling in the nanometer scale due to its ability to suppress short channel effects due to its better gate control, enabling it to achieve performance of high quality and low power. The fin dimen sions play a huge role in the design of a FinFET. Looking at the gadget’s Figure-of merits, the geometries of the transistor are specifically delicate. In this work, a 30 nm Ge based FinFET is designed by parameter omptimization which is achieved through parameter variation using Silvaco software. Literature where Poisson and Schrodinger equations were used to come up with a theoretical analytical quan tum model, is used. The model is based on the quantum mechanical variational approach and accounts for the Ge channel thickness which depends on electric po tential. Since the electrical characteristics are affected by design parameters such as doping concentrations, the most influential factors being on/off current ratio and threshold voltage, were determined through investigation of effects that arose due to variation of multiple design parameters. Systematical investigation is done with the help of graphical data such as current-voltage characteristics and mathematical models which include drain current model. Simulation results show that physical parameters in the form of fin dimensions also influence electrical characteristics of the device. It is also observed that ION/OFF ≈ 106A when the device operating in the range 0.05V≤ VGS ≤ 1V. Properly scaling the drain and source depths and increas ing the doping density for the oxide is mandatory in order to keep short channel effects in the form of DIBL minimal