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| dc.contributor.supervisor | Chuma, Joseph | |
| dc.contributor.author | Kobe, Olebogeng Bone | |
| dc.date.accessioned | 2020-08-14T13:27:46Z | |
| dc.date.available | 2020-08-14T13:27:46Z | |
| dc.date.issued | 2017-09 | |
| dc.identifier.citation | Kobe, O. (2017) A synthesis method for quality-factor enhanced substrate integrated inductor for L-S band, Master’s Thesis, Botswana International University of Science and Technology: Palapye | en_US |
| dc.identifier.uri | http://repository.biust.ac.bw/handle/123456789/148 | |
| dc.description | Thesis (Telecommunications Engineering)--Botswana International University of Science and Technology, 2017 | en_US |
| dc.description.abstract | The thesis presents a flawless synthesis method for designing high quality factor (Q) on-chip microstrip resonator in the form of an inductor based on layout optimisation technique. While the layout optimisation method is already reported in the literature, it was only based on the turns of the spiral inductors with the width of the inner turn narrower than the width of the outer turn. Therefore, since resistivity is dependent of the conductor length and thickness, it is certain that the shorter and/or the thicker the conductor the lower the resistance. Consequently, the low resistance means reduced ohmic losses thus higher performance and higher-Q. Therefore, this optimisation method does not extensively consider ohmic losses relating to resistance of the conducting metal. Conversely, the proposed technique is an extended layout optimisation method developed to reduce ohmic losses of the conducting metal by varying the width of sequential segments, with the inner most segments narrower than the outer most segments of each turn of the spiral inductor. The application of this technique means that the width of each segment is different from that of the succeeding segment, thus making the width of a single spiral turn variable. The technique reduces ohmic losses caused by resistance of segments. It is substantiated that the resistance of a narrow conductor can be reduced by making the conductor short. Likewise, the resistance of a longer conductor can be reduced by making the conductor wider. Two structures, one possessing the traditional characteristics of former technique, and the other possessing the characteristics of the new proposal were built and simulated. The simulation results present higher current distribution in a variable segment width as compared to lower current distribution in a variable turn spiral. The higher the current flow the high the energy stored in the structure hence high Q-factor. The resultant Q-factor improvement observed was over 35% in comparison to the conventional fixed width model. Also a 11.57% improvement was observed compared to the original layout optimisation technique i.e. the variable turn width and spacing. | en_US |
| dc.description.sponsorship | Botswana International University of Science and Technology | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Botswana International University of Science and Technology ( BIUST) | en_US |
| dc.subject | Quality factor | en_US |
| dc.subject | Planar | en_US |
| dc.subject | Microstrips | en_US |
| dc.subject | Current density | en_US |
| dc.title | A synthesis method for quality-factor enhanced substrate integrated inductor for L-S band | en_US |
| dc.description.level | meng | en_US |
| dc.description.accessibility | restricted | en_US |
| dc.description.department | cte | en_US |
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Faculty of Engineering and Technology
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